As the design rule for elements in products such as dynamic random access memories (DRAMs) becomes more stringent, a greater restraint has been imposed on using materials having high resistivity, such as polycrystalline silicon as a gate electrode of the elements. In order to overcome this restraint, many studies for lowering the resistivity of the gate electrode have been carried out.
First, metals, such as tungsten or molybdenum, having a low reactivity with a gate oxide film of, such as, a silicon oxide film, have been investigated for use as the gate electrode. Second, a silicide film of, such as, tantalum silicide TaSi.sub.2 or molybdenum silicide MoSi.sub.2, deposited on the gate oxide film also have been investigated for use as the gate electrode. These methods, however, have problems in that the properties of the gate oxide film may deteriorate and/or the material of the gate electrode may peel off of the gate oxide film by the reaction of the gate oxide film with the gate electrode. Particularly, in case of a ultra-large scale integrated element having a gate oxide film of several tens of angstroms (.ANG.) in thickness, the element can suffer from radiation damage. That is, the stability of the polycrystalline film sometimes cannot be assured with the foregoing methods.
Third, polycides having resistivities as low as the above metals and silicides, as well as stabilities as stable as the polycrystalline silicon film, have been investigated for use as the gate electrode. As for methods for forming the polycides, there is a self-aligned silicide (salicide) method using a chemical vapor deposition (CVD) method or with a sputtering method.
FIGS. 1A and 1B are sectional views illustrating a semiconductor element illustrating a conventional polycide film formed with the salicide method.
Referring to FIG. 1A, a gate oxide film and a layered gate electrode have been formed by forming thin oxide film 11 and polycrystalline silicon film 12 on silicon substrate 10, and by forming polycide film 13 thereon with the salicide method, and subjecting these layers to a patterning.
However, in case the polycide film is formed on a polycrystalline silicon film with the salicide method, the interface between polycrystalline silicon film 12 and polycide film 13 making up the gate electrode is unstable. As a result, problems of agglomeration and penetration of polycide 13 into underlying polycrystalline film 12 may occur as illustrated in FIG. 1B due to a subsequent heat treatment process.
FIGS. 2A and 2B are sectional views of a semiconductor element illustrating a conventional polycide film formed with a CVD method or a sputtering method.
As illustrated in FIG. 2A, in the case of a layered gate electrode having layers of polycrystalline film 22 and polycide film 23 formed on gate oxide film 21 on substrate 20, with the layers formed with a CVD method or a sputtering method, steps may form between polycrystalline silicon film 22 and polycide 23 of the gate electrode and/or polycide film 23 may peel off from polycrystalline silicon film 22 due to shrinkage of polycide film 23 in a subsequent heat treatment process due to the instability of the interface between polycrystalline silicon film 22 and polycide film 23. Moreover, in case the polycide film is used as the gate electrode of an ultra-large scale integrated element on the order of 0.1 .mu.m, there has been a limit in using such a polycide film as a gate electrode due to a sharp increase of the resistivity.
Fourth, a titanium nitride film formed with a reactive sputtering method has been investigated for use as an inactive gate electrode.
As illustrated in FIG. 3A, in case titanium nitride film 32 is used as the gate electrode, the ultra-large scale integrated element having very thin gate oxide film 31 on substrate 30 can suffer from radiation damage. Moreover, the properties of titanium nitride film 32 deposited with a sputtering method may be altered due to immigration of impurities 34 along the grain boundaries between columns of the columnar structured titanium nitride film in a subsequent heat treatment process as illustrated in FIG. 3B.
When the Gibbs free energies of the titanium oxide film and the silicon oxide film are compared, since the energy of the titanium oxide film is substantially greater than the energy of the silicon oxide film, titanium nitride film 32 may react with gate oxide film 31 of silicon oxide in a subsequent heat treatment process. Therefore, a problem may occur in that the gate oxide film is spoiled due to reaction of the titanium nitride film of the gate electrode with the gate oxide film to be altered into a titanium oxide film and a titanium silicide.
Fifth, a composite silicide film has been investigated for use as the gate electrode.
As illustrated in FIG. 4, in order to solve the problem of the third method wherein the polycide film is used as the gate electrode, a composite polycide structured gate electrode is formed by depositing both titanium nitride film 43 on polycrystalline silicon film 42 as a barrier and titanium silicide TiSi.sub.2 film 44 thereon. Reference numbers 40 and 41 in the drawing represent a silicon substrate and a gate oxide film, respectively. However, since the method also utilizes a sputtering method in forming the titanium silicide, like the previous case, the problems of shrinkage and contamination by impurities of the silicide have been caused in a subsequent heat treatment process.
FIG. 5 is a sectional view of a general COB (Capacitor On Bit line) structured DRAM element having bit lines formed of polycide.
Referring to FIG. 5, in general, the conventional COB structured DRAM element has used polycide, for example, tungsten silicide WSi.sub.2 /polycrystalline silicon films 52 and 51, as bit lines. In case the bit lines are formed of polycide, though advantageous in terms of excellent thermal stability, such may have a problem of low operation speed of the element due to the high resistivity of the tungsten silicide film being about 50.about.200 .mu..OMEGA..multidot.cm and the resistivity of the polycrystalline silicon film being about 200 .mu..OMEGA..multidot.cm.
Moreover, the polycrystalline silicon film of the bit line doped with n+ type impurities can form a contact only to n+ type or n- type region 53 or 54. Therefore, in order to form a contact for capacitor 57 to a bit line to p+ type region 55 in a final wiring process, a poor process of etching insulation film 59 at a portion having an aspect ratio of more than 3 should have been carried out.
That is, in case wiring 56-2 and 56-1 are formed with contacts to n+ type region 53 and p+ type region 55, respectively, a contact to region 53 having a substantially smaller aspect ratio than the contact to p+ type region 55 can be formed due to a bit line formed of polycrystalline silicon film 51 and tungsten silicide film 52 on n+ type region 53.
At this time, in case the bit line is formed of a metal, the process can be simple since the bit line can be formed irrespective of the conduction type of the impurity region, but, as illustrated in FIG. 5, in case the bit line is formed of a polycrystalline silicon film, there has been a problem in that the processes are substantially complicated and difficult, since a contact to p+ type region 55 having a much greater aspect ratio may be required.
Moreover, the thermal processes for fabricating the COB structured DRAM element performed at an elevated temperature of over 800.degree. C. repeated several times after the processes for forming gate electrodes 58 and the bit lines is equivalent to a process performed under an elevated temperature such as about 870.degree. C. for 9 hours.
Therefore, an effective barrier layer that can inhibit reaction of the bit line metal with the silicon substrate is required in case a metal like tungsten is used as the bit line material.
Referring to FIG. 6A, for the conventional COB structured DRAM element, titanium nitride and titanium films 63 and 62 have been used as a barrier layer for preventing high temperature diffusion of the bit line tungsten.
That is, in order to prevent diffusion of the bit line tungsten in the processes performed under elevated temperatures after the formation of tungsten bit line 64, a barrier layer formed of titanium nitride and titanium films 63 and 62 has been formed between bit line 64 and silicon substrate 60. Reference number 61 in the drawing is a thick insulation film formed of an oxide film.
However, as has been explained, since the titanium nitride film has a columnar structure with many voids, the barrier layer formed of the titanium nitride film/titanium film can be spoiled as illustrated in FIG. 6B.
Therefore, there has been a problem in that the element can be spoiled due to reaction of the tungsten with the substrate through the spoiled barrier to form tungsten silicide 65.
Moreover, there has been a problem in that the resistivity of the foregoing titanium nitride film deposited with the reactive sputtering method becomes very high (up to about 200-1000 .mu..OMEGA..multidot.cm) due to the grain structure illustrated in FIG. 3B, compared to a resistivity of about 23 .mu..OMEGA..multidot.cm of a single crystal titanium nitride film at room temperature.